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april 2006 dsc-6112/0a ?2006 integrated device technology, inc. qdr srams and quad data rate rams comprise a new family of products developed by cypress semiconductor, idt, and micron technology, inc. 1 18mb pipelined ddr?ii sram burst of 2 idt71p71804 idt71p71604 description the idt ddrii tm burst of two srams are high-speed synchro- nous memories with a double-data-rate (ddr), bidirectional data port. this scheme allows maximization of the bandwidth on the data bus by passing two data items per clock cycle. the address bus operates at single data rate speeds, allowing the user to fan out addresses and ease system design while maintaining maximum performance on data transfers. the ddrii has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. all interfaces of the ddrii sram are hstl, allowing speeds beyond sram devices that use any form of ttl interface. the inter- face can be scaled to higher voltages (up to 1.9v) to interface with 1.8v systems if necessary. the device has a v ddq and a separate vref, allowing the user to designate the interface operational voltage, inde- pendent of the device core voltage of 1.8v v dd. the output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines. clocking the ddrii sram has two sets of input clocks, namely the k, k clocks and the c, c clocks. in addition, the ddrii has an output ?echo? clock, cq, cq . functional block diagram notes 1) represents 18 signal lines for x18, and 36 signal lines for x36 2) represents 20 address signal lines for x18 and 19 address signal lines for x36. 3) represents 2 signal lines for x18 and 4 signal lines for x36. 4) represents 36 signal lines for x18 and 72 signal lines for x36. data reg add reg ctrl logic clk gen (note2) a ld r / w (note3) bw x k k c c select output control w r i t e / r e a d d e c o d e s e n s e a m p s o u t p u t r e g o u t p u t s e l e c t write driver (note2) cq dq (note1) (note4) 18m memory array cq 6112 drw 16 s (note1) sa 0 (note 1) features 18mb density (1mx18, 512kx36) common read and write data port dual echo clock output 2-word burst on all sram accesses multiplexed address bus - one read or one write request per clock cycle ddr (double data rate) data bus - two word bursts data per clock depth expansion through control logic hstl (1.5v) inputs that can be scaled to receive signals from 1.4v to 1.9v. scalable output drivers - can drive hstl, 1.8v ttl or any voltage level from 1.4v to 1.9v. - output impedance adjustable from 35 ohms to 70 ohms 1.8v core voltage (v dd ) 165-ball, 1.0mm pitch, 13mm x 15mm fbga package jtag interface
6.42 2 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range write operations are initiated by holding the read/write control input (r/ w ) low, the load control input ( ld ) low and presenting the write address to the address port during the rising edge of k, which will latch the address. on the following rising edge of k, the first word of the two word burst must be present on the data input bus dq[x:o], along with the appropriate byte write ( bwx ) inputs. on the following rising edge of k , the second half of the data write burst will be accepted at the device input with the designated ( bwx ) inputs. ddrii devices internally store two words of the burst as a single, wide word and will retain their order in the burst. the x18 and x36 ddrll devices have the ability to address to the individual word level using the sa0 address, but the burst will continue in a linear sequence and wraps around without incrementing the sa bits. similarly when reading x18 and x36 ddrll devices, the read burst will begin at the designated address, but if the burst is started at any other position than the first word of the burst, the burst will wrap back on itself and read the first locations before completing. the x18 and x36 ddr ii devices can also use the byte write signals to prevent writing any individual bytes or word of the burst. output enables the ddrii sram automatically enables and disables the dq[x:0] outputs. when a valid read is in progress, and data is present at the output, the output will be enabled. if no valid data is present at the output (read not active), the output will be disabled (high impedance). the echo clocks will remain valid at all times and cannot be disabled or turned off. during power-up the dq outputs will come up in a high impedance state. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and vss to allow the sram to adjust its output drive impedance. the value of rq must be 5x the value of the intended drive impedance of the sram. the allowable range of rq to guarantee impedance matching with a tolerance of +/- 10% is between 175 ohms and 350 ohms, with v ddq = 1.5v. the output impedance is adjusted every 1024 clock cycles to correct for drifts in supply voltage and tem- perature. if the user wishes to drive the output impedance of the sram to it?s lowest value, the zq pin may be tied to v ddq . the k and k clocks are the primary device input clocks. the k clock is used to clock in the control signals ( ld , r/ w and bw x), the address, and the first word of the data burst during a write operation. the k clock is used to clock in the control signals ( bw x), and the second word of the data burst during a write operation. the k and k clocks are also used internally by the sram. in the event that the user disables the c and c clocks, the k and k clocks will also be used to clock the data out of the output register and generate the echo clocks. the c and c clocks may be used to clock the data out of the output register during read operations and to generate the echo clocks. c and c must be presented to the sram within the timing tolerances. the output data from the ddrii will be closely aligned to the c and c input, through the use of an internal dll. when c is presented to the ddrii sram, the dll will have already internally clocked the first data word to arrive at the device output simultaneously with the arrival of the c clock. the c and second data word of the burst will also correspond. single clock mode the ddrii sram may be operated with a single clock pair. c and c may be disabled by tying both signals high, forcing the outputs and echo clocks to be controlled instead by the k and k clocks. dll operation the dll in the output structure of the ddrii sram can be used to closely align the incoming clocks c and c with the output of the data, generating very tight tolerances between the two. the user may disable the dll by holding d o f f low. with the dll off, the c and c (or k and k if c and c are not used) will directly clock the output register of the sram. with the dll off, there will be a propagation delay from the time the clock enters the device until the data appears at the output. echo clock the echo clocks, cq and cq , are generated by the c and c clocks (or k, k if c, c are disabled). the rising edge of c generates the rising edge of cq, and the falling edge of cq . the rising edge of c generates the rising edge of cq and the falling edge of cq. this scheme improves the correlation of the rising and falling edges of the echo clock and will improve the duty cycle of the individual signals. the echo clock is very closely aligned with the data, guaranteeing that the echo clock will remain closely correlated with the data, within the tolerances designated. read and write operations read operations are initiated by holding read/write control input (r/ w ) high, the load control input ( ld ) low and presenting the read address to the address port during the rising edge of k, which will latch the address. the data will then be read and will appear at the device output at the designated time in correspondence with the c and c clocks.
6.42 3 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range symbol pin function description dq[x:0] input/output synchronous data i/o signals. data inputs are sampled on the rising edge of k and k during valid write operations. data outputs are driven during a valid read operation. the outputs are aligned with the rising edge of both c and c during normal operation. when operating in a single clock mode (c and c tied high), the outputs are aligned with the rising edge of both k and k . when a read operation is not initiated or ld is high (deselected) during the rising edge of k, dq[x:o] are automatically driven to high impedance after any previous read operation in progress completes. 1m x 18 -- dq[17:0] 512k x 36 -- dq[35:0] bw 0 , bw 1, bw 2 , bw 3 input synchronous byte write select 0, 1, 2, and 3 are active low. sampled on the rising edge of the k and again on the rising edge of k clocks during write operations. used to select which byte is written into the device during the current portion of the write operations. by tes not written remain unaltered. all the byte writes are sampled on the same edge as the data. deselecting a byte write select w ill cause the corresponding byte of data to be ignored and not written in to the device. 1m x 18 -- bw 0 controls dq[8:0] and bw 1 controls dq[17:9] 512k x 36 -- bw 0 controls dq[8:0], bw 1 controls dq[17:9], bw 2 controls dq[26:18] and bw 3 controls dq[35:27] sa input synchronous address inputs. addresses are sampled on the rising edge of k clock during active read or write operations. sa 0 input synchronous burst count address bit on x18 and x36 ddrll devices. this bit allows changing the burst order in read or write operations, or addressing to the individual word of a burst. see page 9 for all possible burst sequences. ld input synchronous load control logic: sampled on the rising edge of k. if ld is low, a two word burst read or write operation w ill initiate as designated by the r/ w input. if ld is high during the rising edge of k, operations in progress w ill complete, but new operations will not be initiated. r / w input synchronous read or write control logic. if ld is low during the rising edge of k, the r / w indicates whether a new operation should be a read or write. if r/ w is high, a read operation will be initiated, if r/ w is low, a write operation will be initiated. if the ld input is high during the rising edge of k, the r/ w input will be ignored. c inp ut clo ck po sitive outp ut clock input. c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example for further details . c inp ut clo ck ne gative outp ut clo ck input. c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example for further details . k input clock positive input clock. the rising edge of k is used to capture synchronous inputs to the device and to drive out data through d q[x:0] when in single clock mode. all accesses are initiated on the rising edge of k. k inp ut clo ck ne gative input clock. k is used to capture synchronous inputs being presented to the device and to drive out data through dq[x:0] when in single clock mode. cq, cq output clock synchronous echo clock outputs. the rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. these signals are free running and do not stop when the output data is three stated. zq inp ut output impedance matching input. this input is used to tune the device outputs to the system data bus impedance. dq[x:0] outp ut impedance is set to 0.2 x rq, where rq is a resistor connected between zq and ground. alternately, this pin can be connected d irectly to v ddq , which enables the minimum impedance mode. this pin cannot be connected directly to gnd or left unconnected. 6112 tbl 02a pin definitions
6.42 4 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range symbol pin function description dof f input dll turn off. when low this input will turn off the dll inside the device. the ac timings with the dll turned off will be different from those listed in this data sheet. there will be an increased propagation delay from the incidence of c and c to dq, or k and k to dq as configured. the propagation delay is not a tested parameter, but will be similar to the propagation delay of other sram devices in this speed grade. tdo output tdo pin for jtag tck input tck pin for jtag. tdi input tdi pin for jtag. an internal resistor will pull tdi to v dd when the pin is unconnected. tms input tms pin for jtag. an internal resistor will pull tms to v dd when the pin is unconnected. nc no connect no connects inside the package. can be tied to any voltage level. v ref input reference reference voltage input. static input used to set the reference level for hstl inputs and outputs as well as ac measurement points. v dd power supply power supply inputs to the core of the device. should be connected to a 1.8v power supply. v ss ground ground for the device. should be connected to ground of the system. v ddq power supply power supply for the outputs of the device. should be connected to a 1.5v power supply for hstl or scaled to the desired output voltage. 6112 tbl 02b pin definitions continued
6.42 5 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range pin configuration idt71p71804 (1m x 18) 1234567891011 a cq v ss / sa (2) sa r / w bw 1 k nc ld sa v ss / sa (1) cq b nc dq 9 nc sa nc k bw 0 sa nc nc dq 8 c nc nc nc v ss sa sa 0 sa v ss nc dq 7 nc d nc nc dq 10 v ss v ss v ss v ss v ss nc nc nc e nc nc dq 11 v ddq v ss v ss v ss v ddq nc nc dq 6 f nc dq 12 nc v ddq v dd v ss v dd v ddq nc nc dq 5 g nc nc dq 13 v ddq v dd v ss v dd v ddq nc nc nc h dof f v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc dq 4 nc k nc nc dq 14 v ddq v dd v ss v dd v ddq nc nc dq 3 l nc dq 15 nc v ddq v ss v ss v ss v ddq nc nc dq 2 m nc nc nc v ss v ss v ss v ss v ss nc dq 1 nc n nc nc dq 16 v ss sa sa sa v ss nc nc nc p nc nc dq 17 sasa c sasancncdq 0 r tdo tck sa sa sa c sa sa sa tms tdi 6112 tbl 12b 165-ball fbga pinout top view notes: 1. a10 is reserved for the 36mb expansion address. this must be tied or driven to vss on the 1m x 18 ddrii burst of 2 (71p718 04) devices. 2. a2 is reserved for the 72mb expansion address. this must be tied or driven to vss on the 1m x 18 ddrii burst of 2 (71p7180 4) devices.
6.42 6 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range pin configuration idt71p71604 (512k x 36) 165-ball fbga pinout top view 1234567891011 a cq v ss / sa (3) nc/ sa (1) r / w bw 2 kbw 1 ld sa v ss / sa (2) cq b nc dq 27 dq 18 sa bw 3 k bw 0 sa nc nc dq 8 c nc nc dq 28 v ss sa sa 0 sa v ss nc dq 17 dq 7 d nc dq 29 dq 19 v ss v ss v ss v ss v ss nc nc dq 16 e nc nc dq 20 v ddq v ss v ss v ss v ddq nc dq 15 dq 6 f nc dq 30 dq 21 v ddq v dd v ss v dd v ddq nc nc dq 5 g nc dq 31 dq 22 v ddq v dd v ss v dd v ddq nc nc dq 14 h dof f v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc dq 32 v ddq v dd v ss v dd v ddq nc dq 13 dq 4 k nc nc dq 23 v ddq v dd v ss v dd v ddq nc dq 12 dq 3 l nc dq 33 dq 24 v ddq v ss v ss v ss v ddq nc nc dq 2 m nc nc dq 34 v ss v ss v ss v ss v ss nc dq 11 dq 1 n nc dq 35 dq 25 v ss sa sa sa v ss nc nc dq 10 p nc nc dq 26 sa sa c sa sa nc dq 9 dq 0 r tdo tck sa sa sa c sa sa sa tms tdi 6112 tbl 12c notes : 1. a3 is reserved for the 36mb expansion address. 2. a10 is reserved for the 72mb expansion address. 3. a2 is reserved for the 144mb expansion address
6.42 7 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range notes: 1) all byte write ( bw x) signals are sampled on the rising edge of k and again on k . the data that is present on the data bus in the designated byte will be latched into the input if the corresponding bw x is held low. the rising edge of k will sample the first byte of the two word burst and the rising edge of k will sample the second byte of the two word burst. 2) the availability of the bw x on designated devices is described in the pin description table. 3) the ddrii burst of two sram has data forwarding. a read request that is initiated on the cycle following a write request to the same address will produce the newly written data. signal bw 0 bw 1 bw 2 bw 3 write byte 0 l x x x write byte 1 x l x x write byte 2 x x l x write byte 3 x x x l 6112 tbl 09 write descriptions (1,2,3) linear burst sequence table (1) note: 1. sa 0 is the address presented giving the burst sequence a,b. sa 0 ab 0 01 1 10 6112 tbl 22
6.42 8 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range application example sram #1 a ld r/ w bw 0 bw 1 c c k k dq zq a ld bw 0 bw 1 c c k k dq zq r=250 r=250 v t data bus address ld r/ w memory controller return clk source clk return clk source clk r=50 v t r w w w vt =v ref v t v t r 6112 drw 20 sram #4 bw x r/ w ss v t t v r r r r
6.42 9 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range absolute maximum ratings (1) (2) capacitance (t a = +25c, f = 1.0mhz) (1) symbol rating value unit v term supply voltage on v dd with respect to gnd ?0.5 to +2.9 v v term supply voltage on v ddq with respect to gnd ?0.5 to v dd +0.3 v v term voltage on input terminals with respect to gnd ?0.5 to v dd +0.3 v v term voltage on output and i/o terminals with respect to gnd. ?0.5 to v ddq +0.3 v t bias temperature under bias ?55 to +125 c t stg storage temperature ?65 to +150 c i out continuous current into outputs + 20 ma 6112 tbl 05 symbol parameter conditions max. unit c in input capacitance v dd = 1.8v v ddq = 1.5v 5pf c clk clo ck input cap acitance 6 p f c o output capacitance 7 pf c dq dq i/o cap acitance 7 p f 6112 tbl 06 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v ddq must not exceed v dd during normal operation. note: 1. tested at characterization and retested after any design or process change that may affect these parameters. recommended dc operating and temperature conditions symbol parameter min. typ. max. unit v dd power supply voltage 1.7 1.8 1.9 v v ddq i/o supply voltage 1.4 1.5 v dd v v ss ground 0 0 0 v v ref input reference voltage 0.68 v ddq /2 0.95 v t a ambient temperature (1) 02570 o c 6112 tbl 04 note: 1. during production testing, the case temperature equals the ambient tempera- ture.
6.42 10 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range dc electrical characteristics over the operating temperature and supply voltage range (v dd = 1.8 100mv, v ddq = 1.4v to 1.9v) parameter symbol test conditions min max unit note input leakage current i il v dd = max v in = v ss to v ddq -2 +2 a output leakage current i ol output disabled -2 +2 a operating current (x36): ddr i dd v dd = max, i out = 0ma (outputs open), cycle time > t khkh min 250mh z -900 ma 1 200mhz - 800 167mhz - 700 operating current (x18): ddr i dd v dd = max, i out = 0ma (outputs open), cycle time > t khkh min 250mh z -850 ma 1 200mhz - 750 167mhz - 650 standby current: nop i sb1 device deselected (in nop state), i out = 0ma (outputs open), f=max, all inputs < 0.2v or > vdd -0.2v 250mh z -325 ma 2 200mhz - 300 167mhz - 275 output high voltage v oh1 rq = 250 ?, i oh = -15ma v ddq /2-0.12 v ddq /2+0.12 v 3,7 output low voltage v ol1 rq = 250 ?, i oh = 15ma v ddq /2-0.12 v ddq /2+0.12 v 4,7 output high voltage v oh2 i oh = -0.1ma v ddq -0.2 v ddq v5 output low voltage v ol2 i ol = 0.1ma v ss 0.2 v 6 6112 tbl 10c notes: 1. operating current is measured at 100% bus utilization. 2. standby current is only after all pending read and write burst operations are completed. 3. outputs are impedance-controlled. i oh = -(v ddq /2)/(rq/5) and is guaranteed by device characterization for 175 ? < rq < 350 ?. this parameter is tested at rq = 250 ?, which gives a nominal 50 ? output impedance. 4. outputs are impedance-controlled. i ol = (v ddq /2)/(rq/5) and is guaranteed by device characterization for 175 ? < rq < 350 ?. this parameter is tested at rq = 250 ?, which gives a nominal 50 ? output impedance. 5. this measurement is taken to ensure that the output has the capability of pulling to the v ddq rail, and is not intended to be used as an impedance measurement point. 6. this measurement is taken to ensure that the output has the capability of pulling to v ss , and is not intended to be used as an impedance measurement point. 7. programmable impedance mode.
6.42 11 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range input electrical characteristics over the operating temperature and supply voltage range (v dd = 1.8 100mv, v ddq = 1.4v to 1.9v) notes: 1. these are dc test criteria. dc design criteria is v ref + 50mv. the ac v ih /v il levels are defined separately for measuring timing parameters. 2. v il (min) dc = -0.3v, v il (min) ac = -0.5v (pulse width <20% tkhkh (min)) 3. v ih (max) dc = v ddq +0.3, v ih (max) ac = v dd +0.5v (pulse width <20% tkhkh (min)) 4. this conditon is for ac function test only, not for ac parameter test. 5. to maintain a valid level, the transitioning edge of the input must: a) sustain a constant slew rate from the current ac level through the target ac level, v il (ac) or v ih (ac) b) reach at leaset the target ac level. c) after the ac target level is reached, continue to maintain at least the target dc level, v il (dc) or v ih (dc) v il v dd v dd +0.25 v dd +0.5 20% t khkh ( min) 6112 drw 21 v ss v ih v ss -0.25v v ss -0.5v 20% tkhkh (min) 6112 drw 22 overshoot timing undershoot timing parameter symbol min max unit notes input high voltage, dc v ih (dc )v ref +0.1 v ddq +0.3 v 1,2 input low voltage, dc v il (dc) -0.3 v ref -0.1 v 1,3 input high voltage, ac v ih (ac) v ref +0.2 - v 4,5 input low voltage, ac v il (ac) -v ref -0.2 v 4,5 6112 tbl 10d
6.42 12 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range ac test load device r l =50 ? z 0 =50 ? v ddq /2 under test v ref output 6112 drw 04 zq r q =250 ? ddq /2 v parameter symbol value unit note core power supply voltage v dd 1.7 to 1.9 v 2 i/o power supply voltage v ddq 1.4 to v dd v2 input high level v ih (v ddq /2)+ 0.5 v input low level v il (v ddq /2)- 0.5 v input reference level vref v ddq /2 v input rise/fall time tr/ tf 0.3/0.3 ns dq rise/fall time 0.5/0.5 output timing reference level v ddq /2 v 6112 tbl 11a ac test conditions (1) note: 1. parameters are tested with rq=250 ? 2. vddq does not exceed vdd. during ac testing vddq is within 300mv of vdd. input waveform output waveform ( v ddq /2) + 0.5v (v ddq /2) - 0.5v 6112 drw 07 v ddq /2 v ddq /2 test points 6112 drw 08 v ddq /2 v ddq /2 test points
6.42 13 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range ac electrical characteristics (v dd = 1.8 100mv, v ddq = 1.4v to 1.9v, t a =0 to 70c) (3,7) symbol parameter 250mhz 200mhz 167mhz unit notes min. max min. max min. max clock parameters t khkh clock cycle time (k , k ,c, c ) 4.00 6.30 5.00 7.88 6.00 8.40 ns t kc var clock phase jitter (k, k ,c, c ) - 0.20 - 0.20 - 0.20 ns 1,5 t khkl clock high time (k, k ,c, c ) 1.60 - 2.00 - 2.40 - ns 8 t klkh clock low time (k, k ,c, c ) 1.60 - 2.00 - 2.40 - ns 8 t kh k h clock to cl ock (k k ,c c ) 1.80 - 2.20 - 2.70 - ns 9 t k hkh cl ock to clock ( k k, c c) 1.80 - 2.20 - 2.70 - ns 9 t khch clo c k to data c loc k (k c, k c ) 0.00 1.80 0.00 2.30 0.00 2.80 ns t kc lock dll lock time (k, c) 1024 - 1024 - 1024 - cycles 2 t kc reset k static to dll reset 30 - 30 - 30 - ns output parameters t chqv c, c high to output valid - 0.45 - 0.45 - 0.50 ns 3 t chqx c, c high to output hold -0.45 - -0.45 - -0.50 - ns 3 t chcqv c, c high to echo clock valid - 0.45 - 0.45 - 0.50 ns 3 t chcqx c, c high to echo clock hold -0.45 - -0.45 - -0.50 - ns 3 t cqhqv cq, cq high to output valid - 0.30 - 0.35 - 0.40 ns t cqhqx cq, cq high to output hold -0.30 - -0.35 - -0.40 - ns t chqz c high to output high-z - 0.45 - 0.45 - 0.50 ns 3,4,5 t chqx1 c high to output low-z -0.45 - -0.45 - -0.50 - ns 3,4,5 set-up times t avkh address valid to k, k rising edge 0.50 - 0.60 - 0.70 - ns 6 t ivkh r , w inputs valid to k, k rising edge 0.50 - 0.60 - 0.70 - ns t dvkh data-in and bw x valid to k, k rising edge 0.35 - 0.40 - 0.50 - ns hold times t khax k, k rising edge to address hold 0.50 - 0.60 - 0.70 - ns 6 t khix k, k rising edge to r , w inputs hold 0.50 - 0.60 - 0.70 - ns t khdx k, k rising edge to data-in and bw x hold 0.35 - 0.40 - 0.50 - ns 6112 tbl 11 notes: 1. clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 2. v dd slew rate must be less than 0.1v dc per 50 ns for dll lock retention. dll lock time begins once vdd and input clock are stabl e. 3. if c, c are tied high, k, k become the references for c, c timing parameters. 4. to avoid bus contention, at a given voltage and temperature tchqx 1 is bigger than tchqz. the specs as shown do not imply bus contention because tchqx1 is a min parameter that is worse case at totally different te st conditions (0c, 1.9v) than tchqz, which is a max parameter (worst case at 70c, 1.7v) it is not possible for two srams on the same board to be at such different voltage and temperature. 5. this parameter is guaranteed by device characterization, but not production tested. 6. all address inputs must meet the specified setup and hold times for all latching clock edges. 7. during production testing, the case temperature equals t a. 8. clock high time (tkhkl) and clock low time (tklkh) should be within 40% to 60% of the cycle time (tkhkh). 9. clock to c l o c k time (tkh k h) and c l o c k to clock time (t k hkh) should be within 45% to 55% of the cycle time (tkhkh).
6.42 14 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range timing waveform of combined read and write cycles note: 1. if a r/ w is low on the next rising edge of k after a read request, the device automatically performs a nop (no operation.) 2. the second nop cycle is not necessary for correct device operation; however, at high clock frequencies, it may be required to prevent the bus contention. 6112 drw09 k k 1 2 3 ld sa tkhch tkhkl tkhix tivkh tkhax tavkh c c cq cq tchqx tchqx1 tdvkh tkhdx tkhdx d20 d21 d30 d31 tdvkh tklkh tchcqv tchcqx r/ w dq 4 5 67 tklkh tkhkh tkh k h a2 a1 a0 a3 tchqv tchqx tchqv tcqhqv tkhch tkhkl nop read a0 (burst of 2) read a1 (burst of 2) nop (note 1) write a2 (burst of 2) read a4 (burst of 2) q00 q01 q10 q11 q40 q41 8 nop a4 qx1 tchqz tkhkh tkh k h tchcqx tchcqv write a3 (burst of 2) 9 10 tcqhqx (note 1) (note 2)
6.42 15 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range this part contains an ieee standard 1149.1 compatible test access port (tap). the package pads are monitored by the serial scan circuitry when in test mode. this is to support connectivity testing during manufacturing and system diagnostics. in conformance with ieee 1149.1, the sram contains a tap controller, instruction register, bypass regis- ter and id register. the tap controller has a standard 16-state machine that resets internally upon power-up; therefore, the trst signal is not jtag block diagram jtag instruction coding ir2 ir1 ir0 instruction tdo output notes 0 0 0 extest boundary scan register 0 0 1 idcode identification register 2 0 1 0 sample-z boundary scan register 1 0 1 1 reserved do not use 5 1 0 0 sample/preload boundary scan register 4 1 0 1 reserved do not use 5 1 1 0 reserved do not use 5 1 1 1 bypass bypass register 3 6112 tbl 13 tap controller state diagram sram core bypass reg. identification reg. instruction reg . control signal s tap controller tdi tms tck tdo 6112 drw 18 test logic reset run test idle select dr capture dr pause dr exit 2 dr update dr shift dr exit 1 dr select ir capture ir pause ir exit 2 ir update ir shift ir exit 1 ir 0 0 0 0 0 0 1 1 1 1 1 1 1 0 6112 drw 17 0 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 note: 1. places dqs in hi-z in order to sample all input data regardless of other sram inputs. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initialized to vss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 4. sample instruction does not place output pins in hi-z. 5. this instruction is reserved for future use. ieee 1149.1 test access port and boundary scan-jtag required. it is possible to use this device without utilizing the tap. to disable the tap controller without interfacing with normal operation of the sram, tck must be tied to vss to preclude a mid level input. tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected, but they may also be tied to vdd through a resistor. tdo should be left unconnected.
6.42 16 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range part instrustion register bypass register id register boundary scan 512k x36 3 bits 1 bit 32 bits 107 bits 1mx18 3 bits 1 bit 32 bits 107 bits 6112 tbl 14 scan register definition identification register definitions instruction field all devices description part number revision number (31:29) 0x0 revision number device id (28:12) 0x0294 0x0295 512kx36 ddrii burst of 2 1mx18 71p71604s 71p71804s idt jedec id code (11:1) 0x033 allows unique identification of sram vendor. id register presence indicator (0) 1 indicates the presence of an id register. 6112 tbl 15
6.42 17 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range boundary scan exit order (1m x 18-bit) order pin id 16r 26p 36n 47p 57n 67r 78r 88p 99r 10 11p 11 10p 12 10n 13 9p 14 10m 15 11n 16 9m 17 9n 18 11l 19 11m 20 9l 21 10l 22 11k 23 10k 24 9j 25 9k 26 10j 27 11j 28 11h 29 10g 30 9g 31 11f 32 11g 33 9f 34 10f 35 11e 36 10e 6112 tbl 16 order pin id 37 10d 38 9e 39 10c 40 11d 41 9c 42 9d 43 11b 44 11c 45 9b 46 10b 47 11a 48 internal 49 9a 50 8b 51 7c 52 6c 53 8a 54 7a 55 7b 56 6b 57 6a 58 5b 59 5a 60 4a 61 5c 62 4b 63 3a 64 1h 65 1a 66 2b 67 3b 68 1c 69 1b 70 3d 71 3c 72 1d 6112 tbl 17 order pin id 73 2c 74 3e 75 2d 76 2e 77 1e 78 2f 79 3f 80 1g 81 1f 82 3g 83 2g 84 1j 85 2j 86 3k 87 3j 88 2k 89 1k 90 2l 91 3l 92 1m 93 1l 94 3n 95 3m 96 1n 97 2m 98 3p 99 2n 100 2p 101 1p 102 3r 103 4r 104 4p 105 5p 106 5n 107 5r 6112 tbl 18
6.42 18 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range order pin id 16r 26p 36n 47p 57n 67r 78r 88p 99r 10 11p 11 9p 12 10n 13 10p 14 11m 15 9n 16 9m 17 11n 18 11l 19 10l 20 9l 21 10m 22 11k 23 9k 24 9j 25 10k 26 11j 27 9g 28 11h 29 10g 30 10j 31 11f 32 10f 33 9f 34 11g 35 11e 36 9e 6112 tbl 16b order pin id 37 10d 38 10e 39 11c 40 9d 41 9c 42 11d 43 11b 44 10b 45 9b 46 10c 47 11a 48 internal 49 9a 50 8b 51 7c 52 6c 53 8a 54 7a 55 7b 56 6b 57 6a 58 5b 59 5a 60 4a 61 5c 62 4b 63 3a 64 1h 65 1a 66 3b 67 1b 68 1c 69 2b 70 3d 71 2c 72 1d 6112 tbl 17b order pin id 73 3c 74 3e 75 1e 76 2e 77 2d 78 3f 79 1f 80 1g 81 2f 82 3g 83 2j 84 1j 85 2g 86 3k 87 1k 88 2k 89 3j 90 3l 91 1l 92 1m 93 2l 94 3n 95 2m 96 1n 97 3m 98 3p 99 1p 100 2p 101 2n 102 3r 103 4r 104 4p 105 5p 106 5n 107 5r 6112 tb l 18b boundary scan exit order (512k x 36-bit)
6.42 19 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range parameter symbol min ty p max unit note i/o power supply v ddq 1.4 - v dd v power supply voltage v dd 1.7 1.8 1.9 v input high level v ih 1.3 - v dd +0.3 v input low level v il -0.3 - 0.5 v tck input leakage current i il -5 - +5 a tms, tdi input leakage current i il -15 - +15 a tdo output leakage current i ol -5 - +5 a output high voltage (i oh = -1ma) v oh v ddq - 0.2 - v ddq v1 output low voltage (i ol = 1ma) v ol v ss -0.2v1 6112 tbl 19 parameter symbol min unit note input hig h le vel v ih 1.8 v input low le vel v il 0v input rise/fall time tr/tf 1.0/1.0 ns input and output timing reference level 0.9 v 1 6112 tbl 20 jtag dc operating conditions jtag ac test conditions note: 1. the output impedance of tdo is set to 50 ohms (nominal process) and does not vary with the external resistor connected to zq . note: 1. for sram outputs see ac test load on page 12. jtag input test waveform jtag output test waveform jtag ac test load 6112 drw 23 0.9 v 0.9 v test points 1 .8 v 0v 6112 drw 24 0.9 v 0.9 v test points 0.9 v 50 ? t do z 0 =50 ? 6112 drw 25 ,
6.42 20 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range parameter symbol min max unit note tck cycle time t chch 50 - ns tck high pulse width t chcl 20 - ns tck low pulse width t clch 20 - ns tms input se tup time t mvch 5-ns tms input ho ld time t chmx 5-ns tdi input setup time t dvch 5-ns tdi input hold time t chdx 5-ns sram input setup time t svch 5-ns sram input hold time t chsx 5-ns clock low to output valid t clqv 010ns 6112 tbl.21 jtag ac characteristics jtag timing diagram tck tms tdi/ sram inputs tdo t mvch t dvch t svch t chcl t chmx t chdx t chsx t clch t clqv 6112drw 19 sram outputs t chch
6.42 21 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range package diagram outline for 165-ball fine pitch grid array
6.42 22 idt71p71804 (1m x 18-bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range ordering information ?qdr srams and quad data rate rams comprise a new family of products developed by cypress semiconductor, idt, and micron techno logy, inc. ? s power xxx speed bq package bq idt 71p71xxx 250 200 167 6112 drw 15 device type 165 fine pitch ball grid array (fbga) clock frequency in megahertz idt71p71804 1m x 18 ddr ii sram burst of 2 idt71p71604 512k x 36 ddr ii sram burst of 2 corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or sramhelp@idt.com san jose, ca 95138 408-284-8200 408-284-4532 fax: 408-284-2775 www.idt.com
idt71p71804 (1m x 18 x -bit) 71p71604 (512k x 36-bit) 18 mb ddr ii sram burst of 2 commercial temperature range revision history revision da te pages description 0 07/29/05 1-24 released final datasheet a 04/21/06 1-3,7,8,10,13, removed 2mx8 (71p71204) and 2mx9 (71p71104) device options. 16,17,22 9,12,19 clarified vddq maximum value equals vdd. 10 updated idd operating current for x36 and x18 options. 12 added clarification for vddq and vdd values for ac test condition.

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